[jevinskie]

Have you heard of the two process design method? [0]

It makes your port maps super simple (and can change them by editing just one file) and each entity consists of just two processes: one to update the entity's state on clock and the other to generate the combinatorial logic using procedural, not dataflow, programming. When you use procedural, you can step through it with a debugger just like with SW! Makes debugging much easier. Also, using records for the port maps makes the ModelSim waveform viewer much easier to use.

You can see an example of it in a MIPS subset I wrote. [1] Any file with a _r.vhd or _p.vhd suffix is written in the two process style. I'd suggest looking at the ALU and I-cache, they are probably the simplest and cleanest entities.

I like your use of numeric_std. =) I'm surprised by how few times I've seen it used.

[0]: http://www.gaisler.com/doc/vhdl2proc.pdf

[1]:https://github.com/jevinskie/mips--/tree/master/project4/sou...

[inforichland]

Yes, I have seen it, and I have used it a few times. For some types of modules, I really do like how it separates out the state from the logic itself; as a person who started writing firmware first, and then started logic design, the two-process method can make it feel less like software sometimes.

Everything I've read these days says to use numeric_std (I've read the reasons why, and it makes sense), so I just never even bothered using the std_logic_*signed libraries. I'll check out your MIPS project; I'm intending my next project to be a fully pipelined RISC machine :-)