[noobiemcfoob]

Not knowing what a latch is or why it is bad seems like more a failure of the class than an inherent problem with Verilog. There are times when a latch is useful and desired (though most often not and most often a normal flop structure is better).

With hardware design, you have to keep in mind that you are modeling hardware. A language that did it all for you might be nice, but you still have to know what framework you are working in. The simulation/synthesis disconnect is inherent to that. You can think of a ton of structures that seem fine at a code level but just don't have a workable analog in silicon. Synthesis in that sense is just another debug tool.

[adwn]

> Not knowing what a latch is or why it is bad seems like more a failure of the class than an inherent problem with Verilog.

You misunderstood the problem: It's not a problem that you can describe a latch, but that it's so easy to make the mistake of describing a latch instead of combinational logic. It's a common mistake and clearly a failure of the language, because two very different intents are described by very similar code.

> The simulation/synthesis disconnect is inherent to that. [...]

No, you're confusing simulation/synthesis mismatch with non-synthesizable code. The former means that simulation gives you different results than the hardware at runtime, which is a very bad thing and should be avoided wherever possible (that's the point of simulation, after all). The latter is unavoidable to a certain degree if the HDL should be usable for simulation.

[noobiemcfoob]

On latches: From experience, I've never had an issue accidentally defining a latch. Simple guidelines (fully describe any case statements or always have an else statement in if branches, use * from Verilog 2005 rather than trying to list all relevant signals) make it more an issue of typos than true unintentional latches and a basic lint flow will identify them quickly.

While I'd accept that perhaps exposing this so easily might be an annoyance in the language, it is hardly a failing.

Synthesis: Again, from experience, this is an issue with your synthesis flow, not the HDL. Synthesis is absurdly complicated, to the point where any team I've been on has at least one guy where that is the entirety of his job. If the generated netlist breaks simulation when your HDL made it all the way through all other flows, more than likely it's an issue with synthesis.