[adwn]

> It was a huge change from everything I had learned before, I had no idea what a latch was and why it was bad to imply them.

Exactly. VHDL and Verilog make hardware design twice as hard as necessary: first you have to think about what structures you need, and then you have to figure out how to describe it with the inappropriate tools your HDL gives you (in such a way that the synthesis software correctly recognizes your intent).