[jasonwatkinspdx]

That may be true. I think you'd have to look at the numbers to see for sure. The paper uses a virtex 6 with 24GB of DDR on a PCIe card. The evaluation board for one of those is about $2k, though obviously the FGPA itself would hopefully be lower in price. I can't seem to find any open pricing for the virtex line. They say using a larger FGPA would allow addressing more DRAM, but of course, that raises your chip costs as well. You'll have to add to that small volume PCB costs, as well as the cost of the hosting server node.

Compare all that to a $2k 1U Xeon with 32GB of ram and dual 10GbE and the prices aren't that dissimilar. Also one is a research project while the other is a commodity a phone call and fedex away.

My guess would be you'd need the FPGA design in high volume for the costs to work out. So it'd be good as an appliance product for a vendor, but unless you're google/facebook huge trying to build this sort of thing yourself would likely be a boondoggle. The exception is the latency performance: you'd have trouble duplicating that with the commodity server design. So if you're doing HFT or somesuch maybe this is interesting again.

A middle road might be something like the Fast Array of Wimpy Nodes design but with a lot more dram and hacking up the kernel to get you true zero copy io with minimal syscall overhead.