[jbri]

I believe the big reason for the power-efficiency is that it's entirely clockless - the power consumption of an idle transistor is very low compared to one that's switching, and a central clock causes many, many transistors to switch every clock cycle. Being clockless is another way to only pay the power cost for silicon that's actually doing something.

Another thing I've been looking at it for is that the design makes it very easy to bit-bang protocols - if you can't get an off-the-shelf chip to speak a protocol for you, using one of these is far cheaper than sticking an FPGA in there, and is similarly cheaper (and easier to patch later) than getting a custom chip unless you're doing a truly massive run of devices.

[tubs]

While this is somewhat true, it becomes less relevant over time. As transistor size shrinks, leakage and static power loss becomes more and more of an issue.

http://www.ruf.rice.edu/~mobile/elec518/readings/DevicesAndC...

AMULET was an attempt to make a commercial async chip and it flopped pretty early, one of the reasons being interfacing with anything else in the entire world kinda requires a clock.

http://apt.cs.manchester.ac.uk/projects/processors/amulet/

[hershel]

Due to leakage current , for some types of applications it doesn't make sense to make the transistor size shrink.

For example , energy micro, one of the leaders in low power microcontrollers use the very old 130nm process, same as those FA18A chips.