[robomartin]

Depending on timing requirements, device type, operating speed and word width you have to add one or more layers of flip-flops to facilitate timing closure and avoid potential metastability issues.

[zhemao]

Right, but that's true of all CPU instructions. If you already have an ALU capable of doing things like integer multiplication, would adding what is essentially a bunch of chained flip-flops really going to add much more complexity or resource usage?

[robomartin]

I was mostly talking about FPGA's. I don't know the criteria designers use when making decisions about what to add (or not) to a CPU design.