[wmf]

It seems to me that if you've got double the clock, the likely explanation is that half the transistors are switching per clock, and power consumption should be orthogonal to clock/IPC ratio.

Nope; a lot of the latches are switching every cycle, so power is higher at higher frequency. This is what doomed NetBurst-style design.

[deepblueq]

Couldn't a 90nm transistor switch at 8 GHz or so in this kind of application? I'm not sure of the exact numbers, but at 1/16th the area occupied, capacitance is much lower, letting it switch far faster.

Just making up some numbers, how about 30% of gates switch on every clock, and 3x the switching speed for modern gates (it's probably much higher, but I'm being conservative here):

NetBurst: (0.3 * 3) / ((0.3 * 3) + (0.7 * 6)) = 17.6% power

Bulldozer: (0.3 * 4.5) / ((0.3 * 4.5) + (0.7 * 18)) = 9.7% power

Sandy Bridge: (0.3 * 3.6) / ((0.3 * 3.6) + (0.7 * 18)) = 7.9% power

So basically, NetBurst is ridiculous, though that shouldn't be news to anyone. Bulldozer doesn't look to be doing so bad as all that, and the numbers improve if the speed is more than 3x.

(I have no idea what the real numbers are, if someone tells me I'll update this.)