[StringyBob]

> P.S. Bulldozer project was a total horror show, beginning to end.

I'm intrigued. In your opinion what were the pain points - Management? Schedule? Technical? Foundry? Methodology (EDA synthesis vs old school hand-layout etc)? Something else?

All of the above?

[szager]

The whole project was over-scoped and over-ambitious. Flush with the success of K8, AMD decided to undertake a completely new from-scratch processor design. New architecture, new cell libraries, new design methodologies, new tools -- we chucked everything out and started over completely.

It's like AMD had their first taste of champagne with the success of K7/K8, and we immediately got drunk and fell on our face.

I would also like to single out for opprobrium Bruce Gieseke, the technical director of the project, who shoved an utterly impractical and labor-intensive design methodology down our throats, and would not relent even when it became clear how much it handicapped the project. We should have been trying to synthesize much more of the chip from day one.

Over all, the project was plagued by delays, bugs, and dead ends. It was way over budget and well past schedule; in the end, it came to market at least two years too late to have an impact. By the time bulldozer-based products reached market, the technical innovations of the new architecture had already been bested (or at least matched) by Ivy Bridge. And of course, Intel has Haswell on deck; AMD, having poured all its resources into bulldozer, has nothing left in the tank.

But bulldozer was also disastrous for all the resources it leeched away from other projects, and the way it focused the company's energy on a product whose market was at least flat, if not yet shrinking. There were some really promising projects that got cancelled so that AMD could throw more engineering resources at bulldozer.

management: fail

schedule: fail

technical: would have been awesome in 2009

foundry: Working with Global Foundries was not entirely smooth, but it would be inaccurate to lay too much blame here.

methodology: fail++

[StringyBob]

Thanks for the write up. In particular I'd seen comments[1] that seemed to imply big disputes between the old school (highly tuned custom chip layout) vs new school (progress via faster iteration with synthesis/automation) design styles.

[1] e.g. http://www.xbitlabs.com/news/cpu/display/20111013232215_Ex_A... (ignoring the misleading intepretation in the article itself).

[szager]

I worked with the engineer cited in that article. He left the company, on less than amicable terms, pretty early in the bulldozer project. I'll just say he lacks credibility, and leave it at that.