[iamrohitbanga]

That makes sense for most processor architectures. But there are exceptions. The Cell Processor (Sony PS3 Processor) has 8 RISC SPUs. These processors do not have branch prediction logic. This is because they were designed for computationally intensive graphics kernels which are useful for Sony PS3 games. There is a huge performance intensive to avoiding branches on these processors. So many times both routes are taken and then the appropriate value is chosen using a mask instruction. This does not stall the pipeline on the processor.