[s_kanev]

I'm a bit surprised by the workflow. While I agree that hardware description languages are terrible from a software developer point of view, to me Verilog is typically much more tolerable than VHDL. Also, in the last few years, SystemC has been getting much more popular as the high-level step before Verilog/VHDL.

[supahfly_remix]

I wondered the same thing. From the github link, I don't see the advantage of Lava over Verilog or VHDL, both languages designed for describing hardware. Maybe Haskell provides some compiler guarantees?

[dons]

Generally, people use these high-level HDLs, like Lava or Cryptol, because:

- faster design time, as you write less code to get the same things done

- reusable high level specifications

- access to high level optimizations not easily possible on the VHDL level

- easier to formally verify the high level spec matches implementation

(Aside, I used to work for a company that designed and sold these types of toolchains).

[s_kanev]

These are all valid points for high-level languages in general. One can add easier parametrization to the list (high-performing HDL code can be terrible to reparametrize).

I was mostly surprised by the choice of a Haskell-based DSL. I think such languages miss their target audience. Most people writing in an HDL are hardware designers without significant software training (I am fortunate to be a software-turned-hardware person). For them making the jump to, f.e. a functional paradigm (as in Bluespec), is much harder compared to a lesser, more popular evil (C/C++ based DSLs like SystemC or AutoESL).

[supahfly_remix]

Interesting...where do you recommend starting to learn more about these languages (books, open source languages, etc.)?