[roadbuster]

Great project & article. Beyond the use of verilog, I couldn't find a description of the EDA stack. What tooling is used for the physical stages of design: place & route, LVS, DRC, and electrical circuit simulation (SPICE)?

[random__duck]

True, I went over the EDA stack a bit in a previous article here: https://talesonthewire.com/projects/blake2s_hashing_accelera...

This used the librelane classic flow, so it's a lot of verilator, yosys, openroad, opensta, magic and klayout. :)