[jcalvinowens]

> One thing that concerns me is the possibility of on-die ECC interacting with ECC on the motherboard and reducing it’s effectiveness

DDR5 on-die ECC detects and corrects one-bit errors. It cannot detect two-bit errors, so it will miscorrect some of them into three-bit errors. My understanding is that the on-die error correction scheme is specifically specially designed such that the resulting three-bit errors are mathematically guaranteed to be detected as uncorrectable two-bit errors by a standard full system-level ECC running on top of the on-die ECC. But I've never found a real authoritative reference that directly says that.

[cobbzilla]

Very good point. It’s nontrivial but not impossible to determine this, I am very curious!

One nightmare scenario is a 3-bit error being detected as a correctable 1-bit error upstream, resulting in data corruption. I agree it’d be really nice to know that could never happen!

[BobbyTables2]

What about rowhammer attacks ?

Wonder if they could be used to introduce “correctable” errors…

[etbe]

The people designing RAM and motherboards and the people working at JEDEC will of course know more about these things than almost everyone who reads hacker news. But I'd still prefer not to just blindly trust that they do the best things for us and have some documentation available.

Is anyone here good at navigating patent records? I would be surprised if there isn't something to be revealed in a patent but I don't know how to find it.