[tliltocatl]

> I'm starting to get the feeling that there is something fundamentally broken in the RISC-V specification that fundamentally limits performance.

RISC-V is an objectively bad ISA design (a resell of MIPS dropping some of the most ominous features, then trying fix the code density issue with billions of extensions), but x86 is way worse and it didn't prevent Intel from making performant implementations. And RISC-V is certainly not bad in the way that would limit performance (well, maybe code density, but it's not the major issue).

The reality is, ISA matters very little for CPU performance. What really matters a lot is the memory subsystem and interconnect. I. e. good DRAM controllers IP are pricey - way more pricey than ARM cores AFAIK. Not a problem unique to RISC-V - i. e. Altera memory controllers used to be shit as well, not sure if Intel changed anything.

And another issue - there doesn't seem to be all that much money in CPUs any more. Look at ARM's history with high-performance sector.

[snvzz]

>trying fix the code density issue with billions of extensions

Not sure what you're on about.

By the time the spec was first ratified (2019), RV64GC was already the densest 64bit ISA, and it's not even close.

[tliltocatl]

> the densest 64bit ISA

Because all other 64-bits were designed with no regard to density too. On 32-bit (and thats where density matters) it's sill worse then Thumb even with compression extension.

[snvzz]

>On 32-bit (and thats where density matters) it's sill worse then Thumb even with compression extension.

Thumb is really good, but this is no longer true as of late 2021, when bitmanip and the code reduction extensions landed.

RISC-V is currently the most dense 64bit ISA, as well as the most dense 32bit ISA.