[sylware]

Everything pushing forward RISC-V is a good thing (this time I get it right...)

I code RISC-V assembly almost everyday, beyond the major point that it is a NON-IP-LOCKED ISA (unlike arm and x86-64), it feels like it does 'sweet spot' nearly all the time. Namely, I am more into binary specifications which means, if RISC-V is zapped one day, we still have some RISC-V byte code and port to an IP-LOCKED ISA is reasonable.

The hard part: _really performant_ micro-architectures for server/desktop/embedded/mobile on latest silicon process.

The harder part: getting much binary-only 'critical' software running there (for instance desktop video games).

And the super hard part: big mistakes _will be made_, and it is going to hurt ooofely.

[sph]

I have no experience with ARM, but after decades of x86, low-level programming or OS development with RISC-V is such a breath of fresh air. Writing a simulator from scratch for the base ISA is like two days of work tops. I am using RISC-V as the instruction set for a bespoke virtual machine: why design a ISA when RISC-V is simple and modular? Bonus: all compilers can now target my VM.

It will accumulate cruft over the years like all other platforms, but right now, it is a joy to work in.

It’s not just for fun, but I’m betting on it because I hope Europe will finally build its own chips, and there is a good likelihood they will choose RISC-V over ARM; expertise in that field for EU developers might soon be a plus.

[sylware]

Yep, I guess we are many to see what's happening with RISC-V.

The most risk of cruft accumutation is in RVA... which is pursuing some level x86-64/ARM hardware compatibility.

That said intel APX/AVX10.2 is RISC-V for x86-64...