[camel-cdr]

You can see the encoding limitation it in the design on SVE, which only has destructive operations, but MOVPRFX, which is a round about way of doing 64-bit instructions, without doing 64-bit instructions.

[dmitrygr]

When the top perf per watt or perf per MHz machine is RISCV, we'll talk. Until then, lol.

[sylware]

Many here wish for the non IP-locked RISC-V to get performant micro-achitectures for embedded/server/desktop/mobile that on the latest silicon process (without that, you can have a very good micro-architecture, that won't probably make the difference).

If some RISC-V high performance CPU manufacturers are being bought by big hardware actors: either they are scared of its competition and want to scrap it or they want to be part of RISC-V.

[dmitrygr]

False dichotomy. They are also quite possibly aqui-hires which then put the good engineers unto actually useful projects.

[sylware]

This is another way to say they are scared ofe competition and want to scrap them.

[brucehoult]

Self-evidently, you therefore won't be the person building this machine.

[dmitrygr]

Nope. I don’t want to work on systems that self-handicap in dumb and predictable ways. Mistakes happen. But mistakes that were preventable and knowable at design time … they are inexcusable, and RISCV is chock-full of those.

[brucehoult]

I disagree.