[joha4270]

You're not the first person to say so (and I don't mean to dispute it), but I have never been able to find a clear answer for /why/ those processes are incompatible.

Is it built in different silicon, is it physical steps that's incompatible (ie its actually incompatible), is it different physical preparations that needs to be made (making it economically infeasible to combine)

I cannot help but wonder, even if the answer doesn't change anything in my life.

[dlenski]

To add to the other comments…

At a very abstract level, when you're manufacturing DRAM you need to manufacture a lot of circuit elements that have HIGH capacitance, since a DRAM cell is basically a capacitor and the higher its capacitance the less frequently it needs to be refreshed.

On the other hand, when manufacturing logic (CPU/GPU/ASIC) you want to minimize the capacitance of almost all circuit elements, since capacitance introduces delay and switching energy cost.

Nearly everything about the manufacturing processes for DRAM and logic is optimized around this fundamentally incompatible figure of merit.

I worked on the development of Intel's eDRAM process, which was used to integrate DRAM into the CPU/GPU die for Iris Pro embedded graphics from 2013-23. https://ieeexplore.ieee.org/document/6576667/

[jahnu]

https://www.reddit.com/r/Semiconductors/comments/r1dqmw/how_...

A Reddit user explains a bit here.

[pjc50]

Medium ELI5 answer: each company and to a great extent each individual fab has a slightly different recipe, which is known as a "process node". This defines all the fabrication steps, every individual layer and its chemical/physical processing.

This in turn affects the electrical properties: parasitic resistance/capacitance, gate dielectric properties and so on. The dielectric in particular is critically different between DRAM and regular CMOS, because DRAM needs to minimise leakage (as that determines how long the memory lasts between refresh cycles).

Regular factories will retool somewhat between jobs. Because it is quite difficult to finetune a silicon process node, it is more common that a fab will set up for a particular node and then switch to "do not touch or change anything under any circumstances", as doing so may wreck yields.

("different substrate entirely" does exist: that's GaN, for power transistors in phone chargers, and SiC, for even higher power transistors.)

[crote]

The physical structure is completely different. Just compare DRAM ([0]) with compute ([1]). As a result, the production process is completely different.

If you want to know more, the Asianometry youtube channel has some fairly good deep dives, such as [2] going through a decent bunch of the 45nm production process, or [3] doing the same for (early) DRAM.

[0]: https://www.youtube.com/watch?v=Bln-v9LmZ3E

[1]: https://i1.wp.com/semiengineering.com/wp-content/uploads/201...

[2]: https://www.youtube.com/watch?v=zUgy29h0alM

[3]: https://www.youtube.com/watch?v=uPualBNf1nM

[rcxdude]

To expand a little on this: a chip fabrication process is a series of steps from incoming bare wafers to finished chips (potentially multiple wafers get combined into a finished chip, as well). To build up the physical structure of the chip, there are a series of steps where different materials are deposited or grown on the surface, masked through photolithography, and removed in order to shape the structure of the chip layer by layer. Each of these depends on not just what that layer itself requires (material, thickness, resolution), but also on the layers around it, because these steps are not independent: a lot of process design is in finding a way to construct a given chip that means each step is compatible with the others.

What's more, the configuration and flow of the machines used for each step are quite sensitive: you cannot in general just stand up another fab with the same machines, apply the same settings, and hit go on a new chip design and expect any yield: you need to dial in each step, certainly for each process, and likely for each design. This makes switching things around more difficult as well.

So, while in general a fab will have certain common features: spin coaters, photolithography machines, vapor deposition chambers, ovens, etc, the number and specification of each one will vary based on the process, and a production fab will generally not want to change their process drastically, or even to swap between different designs too often.

[wolfi1]

from my basic understanding, memory is much easier to produce then logic chips like GPUs and CPUs, they don't need that many photolithographic layers. while it could be possible to produce memory in fabs for CPUs (though not really desirable in regard to costs) the other way round is more difficult

[cduzz]

DRAM is highly regular and relies on a 1T1C (one transistor, one capacitor) structure. Because those tiny capacitors naturally leak charge, the adjacent transistors must be optimized for ultra-low leakage. That requires thicker gate oxides and higher threshold voltages which makes them slow. Furthermore, digging those deep trench or stacked vertical capacitors requires highly specialized, high-aspect-ratio etching and deposition tools. Also, for DRAM the backend wiring is completely different; DRAM is a giant, uniform grid that only needs about 3–5 metal layers to keep costs rock-bottom while modern logic is highly irregular and complex, requiring 12–16+ metal layers.

Logic processes (CPUs/GPUs), on the other hand, are optimized for raw switching speed. They use thin gate oxides and low threshold voltages, which leak like a sieve. This is fine for a fast processor, but it would wipe out a DRAM cell's charge almost instantly.