[vessenes]

Minkowsky, cool design! Question - the ASIC designers I've worked with over the years have been fairly adamant that integrating memory on package interspersed with logic is very difficult; the general statements run like "those designs always look great on paper, but never tape out properly".

Have you done any hardware tests of this plan? Is this still considered quality advice?

Second q, why start with 28nm? Is the idea that you want to stick with TSMC and be able to shrink? If this does in fact work well, I can imagine wanting to shoot for a smaller process node pretty quickly. Is there some sort of tech / design gap you'll need to figure out as you go?

[minkowsky]

Due to the thermal budget, most of the silicon design is constrained to a 2D layout. So the Memory is competing with logic for layout. Now we stack logic in the backend between metals.

We fabricated 2T0C DRAM arrays with a 3D monolithic structure. That's a must-do.

Why 28nm? Because it's cheap, widely available, and already gives us enough performance to beat Nvidia Vera Rubin. We have a road map, scaling it down. https://www.phantafield.com/whitepaper#6-scaling-roadmap

[robocat]

> 2T0C

2 transistor zero capacitors

See last paragraph (3.) of another comment for context: https://news.ycombinator.com/item?id=48713803

[gfody]

isn't cerebras the pudding proof of this design? it seems like ai chips galore are appearing from the woodwork but cerebras is 10 years down this rabbit hole and poised to dominate

[vessenes]

I believe cerebras is one wafer, not deeply stacked, each core is like half memory half compute by area.