| I think that people are still underestimating the technical merits of Intel's 18A fabrication process. I haven't seen any competitor even try to address the backside power delivery of 18A. I suspect that Samsung,TSMC have something similar and doesn't talk about it. The design rules for the standard cell (sort of corresponding to the die area required by a transistor) for the Intel 18A seem to target dense, high performance designs. That's not a particularly meaningful insight - of course Intel wants to have the highest performance of all the fabs. Intel's packaging expertise used to be a generation ahead, and indeed their server chips currently use a mad mix of chiplets and through-silicon visas for direct stacking, all heaped onto a reticule-limited monster interposer die. All of this expensive complexity might be sustainable as long as Intel can keep its enterprise customers happy. That hasn't turned out too well for them. AMD has found a mass-market winner with mainstream gaming CPU with extra level 3 cache die stacked on top. Compared to Intel servers, it's brutally simple. But extremely effective in its consumer market. But the Intel chiplets and packaging could be a great toolbox for M7 generation of Apple Silicon. Now that the M5 Pro and Max are multi chip packages, they more resemble the Intel and AMD designs, with chiplets dedicated to I/O or GPU. (Speculation and dreams. That's all I got, and I'm writing it in the face of an absolutely psychotic autocorrect on a tablet.) |
They do, just not as hyped up as Intel. TSMC will have it after 20A. Either 18A or 14A. GAA was supposed to be in 3nm but didn't happen due to multiple reasons. So it is now delayed to 20A. Backside delivery was supposed to be 20A and also got pushed back as well.