[monocasa]

Do we have any explanations of what WLCM means that are more industry focused? I couldn't find anything that didn't look like blogspam. And that explanation of the DRAM being on the same wafer doesn't really make sense. For one, at that point there's no "multi chip" part if you're integrating more onto the same die rather than less.

And their explanation isn't really passing the smell test for me for other reasons, for instance the fact that DRAM processes are pretty radically different than bulk logic processes, which wouldn't really let you put it all on the same wafer, much less the same die. Even back in the day when you had eDRAM blocks (like the Xbox 360's eDRAM die), that was really a DRAM process with a bit of logic cells that wouldn't be competitive if they weren't sitting right next to the DRAM blocks.

I could be wrong here though, my examples are more than a bit long in the tooth.

[GeekyBear]

You can start by reading up on TSMC's name for the tech (although there are many versions at TSMC and TSMC isn't the only company packaging chiplets and memory on top of a silicon interposer).

> CoWoS (Chip-on-Wafer-on-Substrate)

https://semiwiki.com/wikis/industry-wikis/cowos-chip-on-wafe...

It's a more advanced update from their older InFO tech.

[craigjb]

The terms to search for are fan-out wafer level packaging (FOWLP) and TSMC InFO. The chiplets come from different wafers and are reconstituted into a molded plastic wafer, allowing multiple die side-by-side. Then multiple layers of wires are built on top, terminating in a BGA.

[monocasa]

Ok, part of my confusion was that it was being presented in contrast to InFO-oS and InFO-PoP, but it appears to mostly be a modified version of InFO-PoP called InFO-M? Because Apple has been using InFO-PoP for almost a decade at this point, starting with the A10.

[tanseydavid]

My astonishment at these manufacturing processes is never-ending.