To my knowledge, there’s nothing on RISC‑V that’s equivalent to WOS in the "from‑scratch, bare‑metal bring‑up" sense (MMU, interrupt controller, exception levels, etc.).
However, there are several advanced Rust projects on RISC‑V, but they focus on higher‑level OS features rather than the low‑level hardware bring‑up. For instance:
These projects are more "advanced" in terms of OS features (processes, syscalls, userland), but none of them do the full low‑level bring‑up that WOS does on ARM64 (not to what I know of).
So the space is still wide open if someone wants to do a true from‑scratch RISC‑V kernel in Rust.
ARM64 ISA is IP locked like x86_64 ISA, I guess with RISC-V the right way(TM) is to write directly in assembly (without abuse of a macro-preprocessor)
That will avoid to be locked into a specific compiler (look at the cancer of gcc "extensions" and linux) and have to deal with compiler generated 'backdoors'.
However, there are several advanced Rust projects on RISC‑V, but they focus on higher‑level OS features rather than the low‑level hardware bring‑up. For instance:
- rCore — teaching OS in Rust: https://github.com/rcore-os/rcore
- TockOS — Rust microkernel with RISC‑V support: https://github.com/tock/tock
- RustSBI — SBI runtime (not an OS): https://github.com/rustsbi/rustsbi
- xv6-riscv-rust — Rust port of xv6: https://github.com/garentyler/xv6-riscv
These projects are more "advanced" in terms of OS features (processes, syscalls, userland), but none of them do the full low‑level bring‑up that WOS does on ARM64 (not to what I know of).
So the space is still wide open if someone wants to do a true from‑scratch RISC‑V kernel in Rust.