[agalunar]

Perhaps worth noting that the number of lines in a cache is often different than the number of rows, which can be relevant for some workloads.

The size of an ordinary cache is rows × ways × size(line), where rows = 2 ↑ num-idx-bits. For example, most Intel 64 and AMD 64 processors use log₂(size(page)) − log₂(size(line)) = 12 − 6 = 6 index bits for the L1 cache*, so an L1 cache with 8-way associativity is 64 sets × 8 lines/set × 64 bytes/line = 32 KB large, and an L1 cache with 12-way associativity is 64 × 12 × 64 = 48 KB large. I remember being surprised to learn that most processors have only 64 rows in the L1 cache!

*So that virtual indexes and physical indexes are identical (so that retrieval of the row can happen in parallel with TLB lookup).