[topspin]

S has never implied Xtensa, and C doesn't imply RISC-V. That's a widely held misunderstanding. S, C, P, etc. are product categories, not ISAs. S devices are high performance SoCs; large feature set, high frequency, not the lowest power or cost.

Just appending 1 to S3 is odd though. This MCU is step change for Espressif. S4 or something would make more sense.

[orphea]

Not saying you're wrong (appreciate the explanation) but S has been Xtensa and C is RISC-V; even if you don't imply, it's how the things have been. And given S2, S3, and C5 are all clocked at 240 MHz, the performance difference is kinda blur.

[topspin]

Espressif is all-in on RISC-V, expanding their portfolio of RISC-V devices where they previously had only XTensa: ESP32-S31 is the first big departure from the coincidental alignment of ISAs within their product structure and definitively ends further debate about what those letter designations mean.

BTW, S3 has an RISC-V core in addition to the XTensa cores. That's the part that's running in deep sleep.

In practice, most Espressif users barely know or care what ISA is in play: they have ESP-IDF and the Espressif libraries papering over the difference for nearly all purposes.

[topspin]

This is how Jeroen Domburg, Espressif Technical Marketing Manager, addressed this matter in a post on hackaday.io:

"We actually never intended the CPU architecture to be part of the name, as for 99.9% of all users, it doesn’t matter: you write your code in C or some other language, and the compiler plasters over any difference in ISA. Available peripherals, supported radio protocols and CPU power and memory are more important."