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by cassepipe 14 days ago
Curious: What does the "imac" stand for in the architecture target name ?
3 comments

IMAC are the RISC-V extensions supported:

I = Base integer instruction set, 32-bit

M = Standard extension for integer multiplication and division

A = Standard extension for atomic instructions

C = Standard extension for compressed instructions

https://en.wikipedia.org/wiki/RISC-V#ISA_base_and_extensions

Thanks.I can't believe they chose non-arcane, memory-friendly letters. Kind of rare in naming hardware I feel (unless it's not ?)
I see you are unfamiliar with `rv64mafdcbvh_zicsr_zicntr_zihpm_ziccif_ziccrse_ziccrse_ziccamoa_zicclsm_za64rs_zihintpause_zic64b_zicbom_zicbop_zicboz_zfhmin_zkt_zihintntl_zicond_zimop_zcmop_zcb_zfa_zawrs_supm_svade_ssccptr_sstvecd_sstvala_sscounterenw_svpbmt_svinval_svnapot_sstc_sscofpmf_ssnpm_ssu64xl_sstateen_shcounterenw_shvstvala_shtvala_shvstvecd_shvsatpa_shgatpa` also known as `RVA23`
rva23 is pretty friendly.

Needn't use the long thing.

Yea, but remove any one of the extensions and you have a distinct arch with a name that is basically just as confusing.

The point I wanted to make is that nowadays a lot of the extensions do not have such a nice (semi) easy to remember name.

RISC-V went wild with the extension naming in the past few years with the recently ratified extensions. The original extensions are all clubbed to be labelled as G.
The core set of extensions has pretty friendly single letters, but the flip side is you run out of letters pretty quickly.

The non-single-letter extensions should make you feel more at home. Like the supervisor instructions. You have Smcntrpmf which helps with benchmarking by pausing perf counters during traps. I think Smcntrpmf just rolls off the tongue nicely.

Then there's a lot of extensions that start with Z followed by a sprinkling of random letters which is secretly an abbreviation you couldn't have guessed. For instance you have your SHA-2 instructions in Zvknha and Zvknhb, since that's the Vector Krypto NIST Hashes.

There are a few lettered extensions to the base RV32I instruction set. e.g.:

* https://docs.riscv.org/reference/isa/unpriv/m-st-ext.html

where did you find it?