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You've made me do even more digging and now I'm even more confused. ATMega328P, data sheet specifically calls out using that it cannot represent full range, ADC = VIN * 1024 / VREF. The STM32F4 datasheet shows an idealised transfer function which is mid-tread, but the "actual transfer function" is sort of a shifted mid-tread (lowest code is larger than a single LSB, highest code is VREF and 1/4 LSB). Other STM32 references I found show that it should follow an ideal mid-tread, unless you are using VADC as your voltage reference. High resolution differential input ADCs are, as best as I can tell, always mid-tread with both end codes representing the positive and negative voltage reference. The best data sheet I've found was for a PIC32, very detailed transfer characteristic diagram. This shows that each LSB is VREF/1024, but also why! The transfer function shows that is is still a mid-tread transfer, but the highest code is assigned to (1023/1024) * VREF, hence the divide by 1024, but it doesn't solve the 1/2LSB end bin problem. This is different to the ideas presented the article, there is no reason a single ended ADC couldn't use mid-tread quantisation with VREF as the end code. What it does show is that by using divide by 256, you are truncating the range and arbitrarily deciding where the end points should be. This doesn't fix any inherent 1/2LSB quantisation uncertainty, which was the main argument against using divide by 255. As you say, in ADCs it's a moot point with all of the other sources of error. |