[danhor]

> Nothing stops someone from taking the free Windows Vivado and making it run on Linux

The EULA and the fact that the linux versior runs faster & has fewer bugs.

> just the device-dependent backend would be a major improvement and the frontend and optimizer could be shared with other toolchains

That's yosys and it's used by smaller commercial vendors.

> or reverse engineering then bitstream format for these FPGAs

Getting the timing is the hard part (+ good routing afterwards). The bitstream format has AFAIK mostly been reversed. 7 series has mediocre support , but US, US+ and Versal doesn't (probably because they're too expensive for personal usage).

[tardedmeme]

You can just ignore the EULA. Nobody is coming to get you.

Sounds like yosys is good. Why is nobody using it? Why are we all hoping for Vivado instead of just using Yosys?

You can extract the timing information from Vivado. Such information is not copyrightable. You should be able to extract timing data and connectivity data from anything supported by the free version. You could also collaborate with someone with a really fast oscilloscope to gather some timing yourself, though that'll be extremely tedious.

Even if you just get the connectivity data and bitstream format and no timing, that's massively useful for less-than-high-speed projects. A single open source developer just has to make a contribution, doesn't have to do the whole thing in one go. The reverse engineering parts are often the most valuable, especially if they require access to hardware.

[danhor]

> You can just ignore the EULA. Nobody is coming to get you.

You can, but it's not gonna gain broad attention.

> Why is nobody using it?

It's used for chips with a good open source backend (lattice, gatemate). But it's non-trivial to integrate with the vivado backend and doesn't bring many benefits when used as such.

> You can extract the timing information from Vivado. Such information is not copyrightable.

Yes

> You could also collaborate with someone with a really fast oscilloscope to gather some timing yourself

No. Especially not fast-fast and slow-slow corners.

> Even if you just get the connectivity data and bitstream format and no timing, that's massively useful for less-than-high-speed projects.

Not really, you need at least a rough worst-case estimate. Otherwise even trivial designs might not work.

> A single open source developer just has to make a contribution, doesn't have to do the whole thing in one go.

A large part (clocks, routing, LUTs, BRAM, IO, a basic timing model) has to work, otherwise it's not really usable.

It's really non-trivial to get to a basic usable point. I would estimate at least 4-5 very experienced people working on this 2-3 years. Nothing impossible, but also not something that easily happens.

[tardedmeme]

> > You can just ignore the EULA. Nobody is coming to get you.

> You can, but it's not gonna gain broad attention.

True I guess nobody ever gave a shit about The Pirate Bay. That project died without gathering a single user.

> > Why is nobody using it?

> It's used for chips with a good open source backend (lattice, gatemate). But it's non-trivial to integrate with the vivado backend and doesn't bring many benefits when used as such.

Sounds like someone should reverse engineer the vivado backend so it's not needed any more.

[raron]

This. If AMD / Xilinx would publish the documentation what you would need to use their chips, probably very few would use Vivado or ISE.