[elevation]

Why couldn't a company committed to mask fabrication and wafer fabrication, in concept, perform these steps daily, or several times daily? Multiple prototype designs could be grouped together so multiple customers can realize a new design instance in the same iteration.

With an appropriate debug core in the same wafer, designers who'd completed a tape-out could connect to their chip well enough to repeat their design-verification tests on this real hardware, remotely even (no need to physically handle the device 'til you're certain it's working.) Once satisfied, customers could promote their design to be bonded out for installation into their PCB.

"Sure thing boss, we'll add an extra USART core to this afternoon's tape out."

[elictronic]

Because you are dealing with the physical world where those different designs have different requirements that can conflict. It’s like saying all software is basically the same, why don’t you just abstract it all and run it on these Raspberry Pi’s.

You can do that, but it’s going to turn out poorly.

[monocasa]

The wafer manufacturing process takes weeks to months after a tape out.

[elevation]

Accelerating this process sounds like a good focus for an SBIR (small business innovation research) RFP.

[pjc50]

A fab is not a small business!

Part of the delay is really just commercial. Fabs are optimized for utilization - throughput, not latency. A fab operator will prefer to queue up a load of work with as few gaps as possible, and your shuttle service run has to fit in one of the gaps. If you're NVIDIA and you've already booked the fab, there might not be so much delay. But not zero.

Nice little backgrounder: https://siliconmasters.co/blogs/our-blog/how-photomasks-for-...

[petsfed]

Just to buttress and embroider around your point that a fab is not a small business:

If there was a realistic way even to go from bare wafers to non-trivial custom chips in a small-batch fashion, you can bet there would be a cottage industry around it. I would love to live in a world where I could manufacture custom silicon as easily as I can manufacture a custom PCB or custom mechanical part.

But as it stands, quick-turn, rapid-proto "micro" fabs are obscenely expensive, to the extent that if you aren't absolutely certain you need the performance gains from custom silicon, justified by years of R&D that confirms the inadequacy of a multi-chip solution, then the idea is killed before any layout engineer is contacted.

Microfabs are either operated by research institutes, or they're booked solid for years, and basically printing money.

[whateverboat]

The closest thing to that cottage industry is IMEC.

[joe_mamba]

IMEC is a lab, not a fab. They have partnerships with all major fabs for driving research forwards and making prototypes and concepts, but they don't manufacture anything there, it's still up to Samsung, Intel or TSMC to try out whatever IMEC comes up with.

They may have lasers, electron microscopes, probes, etc on-site for testing what Intel or TSMC ship them and verify research results, but that's pretty far away from a "cottage industry".

Intel and Samsung are the true "cottage industries" as they do full vertical integration of IP, R&D and manufacturing under the same roof.

IMEC is more like the UN of semi companies, a place for them to come together, talk, share knowledge and results and decide industry standardisation based on that.

[elevation]

> A fab is not a small business!

An SBIR is just a cost effective way for the government to put a number of PhDs/engineers to work on a problem.

[zerohp]

The time from tapeout to first samples is 3-4 months even for the biggest customers of TSMC.

Shorter for a metal only change.

[NooneAtAll3]

> Fabs are optimized for utilization - throughput, not latency

I remember hearing some company trying for the speed

[vitally3643]

Accelerating the process is an incredibly obvious desire for literally everyone in the industry and there are already gobs of money being put into R&D.

The fact of the matter is that we're dealing with physical and chemical processes. It simply takes time for atoms to move across space. In many steps of the semiconductor fab process we are literally building up the chip by single-atom thick layers.

There's very finite limits to how fast you can throw atoms at a substrate. There are finite limits to how much time a photoresist must be exposed. There are finite limits to how fast chemicals can etch the surface. You can only saw a wafer so fast, you can only physically transport dice through space so fast.

These are problems that the entire industry wants to solve. These are problems at the bleeding edge of physics. This is not something a startup is going to solve, purely because you need to already have an entire semiconductor fab to iterate in.

[phlipski]

There are startups trying to reduce the time/cost of chip-fab. Atomic Semi is one. Most of the big players have shuttle services which one can use to put a small chip on for fabrication for not a lot of money ~ $10k for a few chips. Tiny Tapeout acts as an OshPark or JLC PCB for chip design using 2 different fabs - skywater's 130nm and IHP's 130nm node. Wafer.space uses Gobal Foundries 180nm (~ $7 per 20mm^2 chip).

At the end of the day the industry has evolved and optimized to stamp out millions of chips a year with very little defects. However that requires a fairly hefty upfront commitment in design/verification time along with a capital commitment to make enough chips to get economies of scale. This breaks down when trying to build small volumes of chips quickly. It's like trying to turn an oil tanker quickly....

[jimmyswimmy]

The iteration cycles are limited necessarily by the time between tapeout and getting chips off the line to a testable state. Maybe there's a little room to get an in-wafer test probe system built at the fab if each die has a standard pad layout, which would speed up the 'testable state' part of that timeline. But if your timeline is weeks (if only!) to months, there's little utility in being able to make incremental changes on a daily basis.

Plus, the only way fab costs become achievable are MPW runs which don't have adequate demand for multiple daily runs. The ones I've used run a few processes each month, rotating between most of them on a bimonthly to quarterly basis. They just don't fill up fast enough. But I'm small time fabless so maybe I'm missing something.

[IshKebab]

> Multiple prototype designs could be grouped together

They do this, it's called a multi-project wafer (it's on Wikipedia). It doesn't help with lead time of course. As far as I know tape-out cost is a lot cheaper (if your design is microcontroller-scale) but still in the $100k+ region.

[bee_rider]

I sort of expected this to happen with tightly coupled customer-customizable chiplets inside a single package, instead. But it seems that packaging is also better left to Intel and AMD, I guess.