[lpribis]

Are you seriously suggesting hobbyists should tapeout an ASIC instead of use an FPGA?

1. For one-off designs (quantity=1) ASICs will never beat a high end FPGA on unit price.

2. As a hobbyist, you want to EXPERIMENT. You cannot do that with an ASIC. Hobbyists want to do something simple, test it on real hardware, and slowly build up from that. I don't have the time nor expertise nor motivation to spend months writing verification to get it right the first time for a tapeout.

"Just use a microcontroller"... I will concede that microcontrollers do cover 90% of hobbyists use cases (that number increasing by the day). But for hobbyists sometimes you want to learn HDL or digital logic or computer engineering. You can do this hands on with a FPGA much more effectively than in software.

> It's probably cheaper for them to maintain Windows for one reason or another.

They already need to maintain the Linux build for all the other paid tiers?? These are the same software with different features locked behind a license key. It costs them NOTHING to keep the build enabled for free tier.

[ua709]

> Are you seriously suggesting hobbyists should tapeout an ASIC instead of use an FPGA?

No. I said the low-end of FPGA sales is getting eaten by microcontrollers and the high-end of FPGAs sales is probably about to get eaten by custom ASICs.

Although the cost of making an ASIC is high, in the larger nodes it's not that high, and getting ever cheaper at FPGA performance levels and logic densities. FPGAs are terribly inefficient with their HW they're very easy to beat with an ASIC. They only get away with it because the NRE today is lower. But it's not an order of magnitude lower and I'm not sure how much longer that will be the case in nodes at 28nm and larger based on what I know Universities pay in tape-out classes.

Will there be very low qty projects where the NRE of developing an ASIC overwhelms that of an ASIC, sure. But will there be enough business in that niche to sustain the business of AMD, Intel and Lattice? Not obvious.

And I don't think the FPGA hobbyist market of people who "want to learn HDL" spends enough money to affect what's coming and this decision from AMD reflects that.

> 1. For one-off designs (quantity=1) ASICs will never beat a high end FPGA on unit price.

Never say never. These guys were able to convince investors you're wrong about that. :)

https://atomicsemi.com

P.S. If you're a hobbyist who wants to make an ASIC... https://www.tinytapeout.com

[hardolaf]

> No. I said the low-end of FPGA sales is getting eaten by microcontrollers and the high-end of FPGAs sales is probably about to get eaten by custom ASICs.

You have absolutely no idea what an ASIC costs compared to a FPGA. A FPGA that can compete with a tinytapeout chip costs a few dollars at most in extremely low quantites. Something high performance would need probably TSMC 12nm or similar at a minimum. At that point, you're talking $1M+ between licensing fees and direct costs to just go on a shuttle. If you want to make your own higher volume run or can't wait for shuttle spot, you're looking easily $5-10M minimum for your first 6 wafers. Comparatively, FPGAs competitive with TSMC 12nm run from a few hundred dollars up to several thousand dollars each. So for low volume, they're very competitive.

[imtringued]

Are you sure you actually know what you're talking about?

FPGA unit costs keep doing down and they usually tend to use a recent manufacturing process. Meanwhile the fixed NRE costs of ASICs keep going up the more advanced the manufacturing process is.

An FPGA consists of non programmable logic components such as DSPs, block RAM, NoCs, SERDES/configurable IO, that keep scaling with the manufacturing process.

If you try to replicate this with an older process to cut costs, you will have an area and energy efficiency penalty.

This means that FPGAs have become more relevant over time.

[thijson]

I'm not sure it's quite as clean cut as you say. FPGA's have a 10x penalty in area due to the extra routing wires they need.

Also, it seems like the node that Xilinx has been using lately (28 nm) isn't as cutting edge as it used to be.