[rbanffy]

Dream big. Imagine what we could do with a 5 GHz 6502.

Of course, the memory would need to be on the same die to be able to function at that speed, but my Apple //e had a full megabyte of RAM (in addition to the 64 on the motherboard) and, IIRC, Apple’s bank switching scheme could accommodate up to 16 megs. The chip would be mostly SRAM.

Talking to anything outside the chip would slow things down considerably though, and using one in place of a real 6502 would be comically weird. It’d feel like a machine that spends 99.999999% of the time waiting for IO.

Which, amusingly, feels the opposite of mainframes, where the machine appears to never have to wait for IO.

[LocalH]

I think that would be approaching diminishing returns long before getting to 5GHz. If the only real requirement is "you can write a new value to any register on every cycle" then you need nowhere near that level of overshooting. 20MHz might not be enough (I only mentioned that value because there is an actual commercial product, the SuperCPU, that brought 20MHz 65816 to the C64/128), but 48 or 50MHz might fully cover that. Maybe 60MHz if you want to do other processing on lines where you have to slow down to communicate with the rest of the hardware (which requires slowing down to bus speed - even the base-level C128 could not use 2MHz mode with the VIC-IIe display enabled, as the extra 2MHz cycles stomped on the bus, making the VIC-II display what was essentially open bus).

[rbanffy]

Mine was never an exercise in practicality - it would be ridiculous to implement, and complete overkill.

OTOH, I wonder if someone would build something like this - a 6502/65816 with lots of SRAM and system-bus compatible timings - using the cheapest commercially available foundry, how much could it cost.