[gpderetta]

There is really no such a thing as cacheline locking per-se. As far as I understand, the coherence protocol guarantees that the cpu can hold a cacheline in the exclusive state for a certain set amount of cycles, which is enough to write the top element of the store buffer into it. Making sure that the two cachelines are available at the same time would add either significant complexity to the coherence protocol, which is already one of the most complex bits of the system and very hard to validate, or force a potentially unbounded retry/backoff loop with no guaranteed forward progress.