[snvzz]

RISC-V is an ISA.

There's nothing inherently slow about it, anymore than there is anything inherently slow about x86 or ARM.

High performance microarchitecture implementations are definitely possible. Some of them are available for licensing.

At least one of them (Tenstorrent Ascalon) has been tapped out into a chip and will show up in development boards later this year.

[badgersnake]

If you can’t buy a fast one, then it’s slow.

It might not be slow forever, but it’s slow now. I’d love to see an open ISA that is fast. But I don’t understand why the industry decided to start over with RISC-V when the compilers and toolchains and chips already existed in power land.

[snvzz]

>If you can’t buy a fast one, then it’s slow.

Shrug. The first RVA23-compliant chips are coming soon.

spacemiT K3 imminent (likely shipping boards this month) and Tenstorrent Ascalon (via Atlantis SoC devboard) this summer. These won't be the fastest CPUs available, but they'll meet the "fast enough" criteria for many uses and users.

Multiple parties including Tenstorrent expect performance parity with the ARM and x86 offerings available at the same time by 2028. Note performance is mainly gated by access to latest fab nodes, which comes with costs that necessitate serious volume. They expect to be there by then.

>But I don’t understand why the industry decided to start over with RISC-V when the compilers and toolchains and chips already existed in power land.

The rationale was documented in the "Instruction Sets Should Be Free: The Case For RISC-V" paper[0].

Note OpenPOWER is mentioned but is not in the comparison. The reason for that is simple: RISC-V predates OpenPOWER. It was an obvious reaction to RISC-V, and they were too late, as RISC-V already had the industry's attention. Furthermore, Open is a lie; payment to IBM is required in practice.

0. https://www2.eecs.berkeley.edu/Pubs/TechRpts/2014/EECS-2014-...