[ahartmetz]

The required computing resources double at every branch where you take both paths, and if you speculate ahead by 100+ instructions, with let's say up to 20 branches, it gets way out of hand.

I could see CPUs sometimes taking both paths for close, hard to predict branches. Does anyone have information on that?

[tyjo99]

I believe the way things are currently trending is that architectures might turn some short hard to predict branches into predicated instructions instead (similar to x86 CMOV or some ARM conditional execution instructions). Outside of short branches the overhead for loading up to 2 instructions for every 1 that gets executed can be too costly. Branch predication on SIMD/SIMT instructions is already the way things work for GPUs and AVX256/512 from my understanding.