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by brucehoult
87 days ago
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Very interesting. The first question has to be: why? I don't see any rationale or explanation of the thinking. Is it purely an exercise? Exploration? Is there some algorithm space in which it has an advantage over binary? Is there a compiler? How does it compare on Dhrystone or Coremark per LUT compared to a RISC-V core of similar size on the same FPGA? |
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There are many reasons. The main one is that no architecture exists that models such a complex ternary processor. At most, there are "on paper" implementations of much less complex architectures; no one has addressed the problem at this level. Having a complete architecture and its hardware implementation now allows us to start developing software on something other than an emulator.
> ---- I don't see any rationale or explanation of the thinking. Is it purely an exercise? Exploration? Is there some algorithm space in which it has an advantage over binary? > -----
No, it's a processor that's available now, both the current hardware implementation (on FPGA) and the Verilog/VHDL description for implementation on other architectures (ASIC?), as well as the specifications made available under license.
>---- Is there a compiler? >----
Hmm, but I mentioned it in the paper; currently, a working cross-assembler (obviously) and a high-level language based on Rust are being designed/built.
>---- How does it compare on Dhrystone or Coremark per LUT compared to a RISC-V core of similar size on the same FPGA? >----
This is an interesting question; the answer is: currently, no. We intend to provide (soon) comparative tests of this type.