[ryzvonusef]

original link in chinese, here is a google translate link:

https://money-udn-com.translate.goog/money/story/5612/939845...

The source is a Taipei based journalist:

https://x.com/dnystedt/status/2036231434722222447

    > Tesla’s TeraFab has launched a talent war in Taiwan via job postings seeking senior chip experts (Process Integration Engineers) with over 10-years of experience, media report, adding its 2nm fab plan aims directly at TSMC. Chip engineers are already in short supply in Taiwan – like nearly everything chip related – and industry insiders worry the ‘Musk Halo Effect’ will draw local talent.

[ryzvonusef]

Here is Elon Musk's take on this attempt:

https://x.com/elonmusk/status/2035743704322023820

    > Given that several companies make advanced chips, but no companies have ever made fully reusable rockets or achieved SpaceX scale, I think Starship is harder, but we shall see.

    > Terafab will technically be two fabs, each making only one chip design. This greatly simplifies process flow and allows more linear, adjacent movement of the FOUP. 

    > A super high production rate allows us to test very quickly what steps can be deleted, simplified or sped up, even after the design is fixed. Current fabs are extremely conservative, operating on rigid historical heuristics, which are mostly, but not all, correct. 
 
    > Anything that is a rate limiter at the machine level means that machine will be redesigned, unless already at limit of physics. 

    > Having new iterations of a chip design be produced every day in the research fab (with <7 day lag) means being able to try out many high risk, high return ideas.

    > Etc

    > In any event, there is no other way to reach extreme scale, so either we make Terafab or we will be stuck at the ~20% chip/memory output growth per year of the current industry.

and here is a reply countering this that might provide some insight:

https://x.com/ContrarianCurse/status/2035753377053766134

    > First of all, you can’t turn iterations for 6-8w at 2nm, there is 1k+ steps, can’t speed up dep or EUV any further 

    > “I’ll just delete steps”. Those steps are ruthlessly optimized in surface of reducing defect density and boosting yields - which is critically important with this type of capital intensity 

    > Even TSM took 3y to ramp 2nm and that is with essentially a monopoly on the talent base to pull it off +40 years of accumulated know-how and recipes 

    > This is quite literally impossible. Better off spending that capital on prepays for capacity