[stavros]

Wait a minute, why can't I reply to bunnie's top-level comment? Anyway, here's what I wanted to say:

Adding your CPU to another company's silicon is a genius move, well done. I wonder why companies don't sell their spare die space to others, is it because of trust/risk?

[bunnie]

Crossbar is unusual to start with in that they wanted to do open RTL - so for starters, there's to a first order no companies even willing to discuss open RTL designs. Beyond that - mainly risk. I had to pinky swear that whatever I added would not break the chip, cause timing closure issues, delay the schedule, consume too much area or power, impact yield, I had to run my own validation and review program while meeting their dev methodology, etc. etc. I had to exercise an enormous amount of self-restraint to not push harder and do more interesting things as it was. It's very hard to build up inter-personal trust, and they had to take a calculated risk letting a schmuck like me potentially foul up a multi-million dollar mask set. Hats off to them for making that bold decision, it would have been easier to say nope, too risky, no benefit, cut it from the code base.

[jcgrillo]

I'm basically ignorant of this entire space--I have mostly worked on SaaS products--so please forgive the question if it's too naive but as (the first?) someone who has just experienced this new and rare way of bringing a design to life are there any obvious process/tooling/whatever improvements you noticed that might make it less risky (and therefore less rare)? Reading your blog posts, the crowd supply materials, Xous docs, etc the burning thought at the front of my mind has been "there needs to be a lot more of this". Is there a path towards that?

[bunnie]

There's actually a whole space of shared-mask tapeouts. You might have heard of TinyTapeout [1]/LibreLane [2] and the general concept of "MPW" masks - multi-project wafer masks. These effectively share cost among hundreds of developers, bringing the cost of a tape-out down.

If you're lucky enough to have an affiliation with certain institutions, there are programs that basically give academics the experience I had for a nominal fee. TSMC has a finfet program [3] which powers Soclabs [4] to provide an environment that exceeds Baochip's capabilities. If you look through [4] notice the block that says "Users' HW circuits" - that's basically what my logic is on Baochip. The problem with these is you need to be academic and I think there isn't a clear path to commercialization, and of course lots of NDAs. China also has a program called "One Student One Chip" [5] where students can tape out quite sophisticated SoCs as part of their course work.

It's probably just a matter of time before these academic programs yield a commercially compelling chip, and then that would pave a path for a transition program from the academic program to industry.

Another option is, if Baochip is quite successful, it in itself could serve as a "proof point" that may encourage other companies to allow hitchhikers. When the co-designed IP works, then it's a sales upside for the company, so there is some incentive alignment.

The trick is figuring out how to mitigate the possibility that the IP doesn't work, and bridging the gap between people with ideas and people with tape-out experience. I'm lucky in that in my first jobs out of college I did a deep dive into silicon, even designing custom transistor and standard cells for a bespoke nanophotonics PDK that I helped to develop, so I had the shared language to communicate with both classic chip companies and open source community.

There's an enormous cultural gap between the chip community and the open source community, but everyone's curiosity in this thread and participating in this dialog with questions like yours helps close that gap and thus manifest more hitchhiking opportunities in the future.

[1] https://tinytapeout.com/

[2] https://github.com/librelane/librelane

[3] https://www.tsmc.com/english/dedicatedFoundry/services/unive...

[4] https://soclabs.org/project/tsri-arm-cortex-m55-aiot-soc-des...

[5] https://ysyx.oscc.cc/en/project/intro.html

[jcgrillo]

Thank you for the references this is absolutely fascinating stuff.

[drob518]

Having paid for multi-million dollar mask sets for ASICs before, I can confirm that this would take a lot of trust on Crossbar’s side. Great job on working with them.

[stavros]

Yeah, true, it's all downside for them for this, basically. Still, there must be some price for which companies will let other companies use die space, but maybe that price is higher than just doing the thing yourself...

[bunnie]

In the space of possibilities this can be abstractly thought of as a Caravell [1] harness gone wild. But if you had to price access to the project in a commercial sense, then, the pricing is going to be quite high. Because it's not just the cost of the masks - there's a whole lot of talent and skill in the team that does the "backend" processing. That is, once the RTL is done, it goes through multiple passes of place/route/timing, ATPG, DRC, LVS...and that's just to get to the tape-out. After that there's still more to do with the chip probe, packaging and reeling.

The open-source argument is that if we could make that back-end part more transparent, then, we could improve the tooling and thus decrease the labor. But, even a single mistake at these backend steps can scuttle a whole mask set. The methodology is incredibly incremental, scripts are handed down for generations and there are magic settings in them that make things "just work" and nobody quite remembers why or how but it was probably a lesson learned the hard way so we just leave it that way. And it's not just the money - the iteration time through a fab is months. So you have to be a bit careful about prioritizing your experiments and your risk budget when trying to make progress in this field.

I am lucky in my case because what I want to do aligns with their original commercial interests, so the strategic benefit makes things worth the tactical risk. Frankly a big part of the project overall was just figuring out how to scope things so that we both came away reasonably satisfied in terms of risk and outcomes. Would I like things to be more open? yes. would I liked to have put an opentitan core in there? yes. Would I have been able to take advantage of more back-end support to do a faster CPU? yes. But, we had to constantly balance tactical risks, and even if I don't agree with all their decisions, I have to respect their experience.

[1] https://github.com/efabless/caravel

[stavros]

That's very informative, thank you.

[jasonwatkinspdx]

> Wait a minute, why can't I reply to bunnie's top-level comment?

The powers that be here think they've found a bunch of "hacks" to curb off low quality comments.