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by userbinator
99 days ago
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I don't know if that construction might allow for a more efficient transistor count and it's totally impractical - 1KHz clock speed, 1-bit ALU, etc. - for almost any purpose, but it is technically a RISC-V implementation significantly smaller than 26K That sounds like a microcoded RISC-V implementation, which can really be done for any ISA at the extreme expense of speed. |
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Maybe other CPU's have it as well, though I do not have enough information on that.