Show HN: RISCY-V02: A 16-bit 2-cycle RISC-V-ish CPU in the 6502 footprint

[mysterymath]

Finally finished my little CPU project, RISCY-V02. I built it (with Claude) to challenge the notion that the 6502 was a "local optimum" in its transistor budget. Given the constraints of 1970s home computers (~1 MHz DRAM, so raw clock speed doesn't help), could RISC have been a better design choice? This design argues yes: pipelining, barrel shifters, and more registers beat microcode PLAs, questionable addressing modes, and hardware BCD.

Highlights:

8x 16-bit general-purpose registers (vs 3x 8-bit on 6502)

2-stage pipeline (Fetch/Execute) with speculative fetch

61 fixed 16-bit instructions

2-cycle interrupt entry (vs 7 on 6502)

13,844 SRAM-adjusted transistors (vs 13,176 for 6502 on same process)

1.0-2.6x faster than 6502 across common routines

GDS viewer: https://mysterymath.github.io/riscyv02-sky

Tiny Tapeout Shuttle Entry: https://app.tinytapeout.com/projects/3829

[jonjacky]

Impressive project! But I have question:

The Highlights section near the top of the README says:

13,844 SRAM-adjusted transistors (vs 13,176 for 6502 on same process)

But the Wikipedia article on the 6502 says it only had 3,510 transistors, and says the Monster6502 was built with 3,218 discrete transistors.

Why the discrepancy?

[mysterymath]

To me, it's plausible one might be able to make a similarly small RISCY-V02 on a 70s Rubylith NMOS process with dynamic logic, using pass transistors and tristate busses, all laid out by hand. But I definitely can't do that, and even if I could, I'd have no way to validate that it actually works.

Best I could do was an A/B comparison on a modern process: a clean Verilog model of RISCY-V02, and a clean Verilog model of a 6502, both run through a modern synthesis process for TinyTapeout. Same slosh, inoptimality, and behavior. So, this is a static CMOS design, like the 65C02, on a modernish process node. That being said, the 65C02 had around 11K transistors, so we're not too far off.

This establishes horseshoes and hand grenades plausibility, but basically nothing else. But, it's also a pretty nifty CPU design if I do say so myself!

[jonjacky]

Thanks, I see. In your README you do briefly mention static vs dynamic, NMOS vs CMOS, and 6502 vs 65C02 but I didn't appreciate those could make a 3x difference in the transistor count.

I agree it's a nice CPU design, and the whole project is quite impressive. Will Tiny Tapeout make you an actual chip that you can run?

I'm curious about how you used Claude. Is the CPU design itself completely handmade, or did Claude fill in some details? Did you use Claude for both the Verilog code and the Python emulator and test code? Did you provide Claude with some of your own hand-written code to demonstrate the style you wanted and get it started?

[mysterymath]

TT will either make me a chip I can run, a chip I can run with some workarounds, or garbage. Only time will tell!

As for Claude, honestly, as a partner. We bounced ideas off each other, while I provided overall direction for the project. It was finishing up a design I had started and aborted last year, but we did build this from scratch. I had some good ideas, Claude had some good ideas, but Claude did almost all of the actual grunt work. Looking back, Claude's tactical decisionmaking was often better than mine, but my strategic decisionmaking was far superior. I would also occasionally have to interject when it was "freaking out" and offer a sounding board to help it solve whatever problem it was working through.