[kop316]

Ohh neat! A generalized version of this was the topic of my PhD dissertation:

https://kilthub.cmu.edu/articles/thesis/Modern_Gate_Array_De...

And they are likely doing something similar to put their LLMs in silicon. I would believe a 10x electricity boost along with it being much faster.

The idea is that you can create a sea of generalized standard cells and it makes for a gate array at the manufacturing layer. This was also done 20 or so years ago, it was called a "structured ASIC".

I'd be curious to see if they use the LUT design of traditional structured ASICs or figured what what I did: you can use standard cells to do the same thing and use regular tools/PDKs to make it.

[fho]

I think their "4-bit multiplier with a single transistor" bit is hinting at them using transistors in the sun-threshold regime.

[kop316]

So something that you can do with PDKs is add your own custom standard cell and tell the EDA tools to use them. This is actually pretty smart, this way you can use most of the foundry cells (which have been extensively validated) and focus on things like this "magic multiplier", that you will have to manually validate. This also makes porting across tech nodes easier if you manage only a handful of custom cells versus a completely custom design.

(I have my guesses as to what that is, but I admittedly don't know enough about that particular part of the field to give anything but a guess).

[fho]

My "only" experience here is designing ASICs for Neuromorphic Chips. We used sub-threshold exclusively for linearity and energy reduction. No standard cells for us