[musicale]

> In all of the material (two textbooks and numerous handouts) there was no mention of the obvious similarities to Ada

Really? That's kind of the point of VHDL, isn't it? (vs. Verilog's unholy combination of C-like syntax with begin/end blocks, etc.)

VHDL also inherits Ada's module style, designed to have different implementations of the same thing (and verbosity, where it seems like you often have to say the same thing repeatedly, for better or for worse - more type checking at the expense of more typing at the keyboard.)