[rep_lodsb]

The 80186 and NEC Vxx chips - and of course also the 286 - could already do mul/div in one cycle per bit (+ some overhead for the microcode). What they didn't have was the early-out optimization.

The three-operand form of IMUL also already existed on those processors.

>This wasn't just an incremental upgrade—it was the foundation that would carry the PC architecture for decades to come.

AI?

[csmantle]

> AI?

Probably not; this point is well justified by both theory and practice. Supporting suitably larger operands is indeed what naturally comes following the increase of computation demands.

One point I do differ from the author is that register width don't necessarily correlate with the size of address space. Even 8bit machines can address a large space by splitting apart the logical address and using multiple registers. Likewise, having a wide register does not imply the same address width.

[jecel]

The naming of processor sizes is the subject of debate. I call a "pure 8 bit processor" one that has 8 bits for both data and addresses. Like the Kenbak-1. But these are so rare and educational rather than practical that it is very reasonable to call hybrid 8 bit / 16 bit processors just "8 bit".

This use of sloppy terms shouldn't make us forget that they are using an address extension trick, just like all those 16 bit processors that wanted to go beyond 64KB (for byte addressed such as the PDP-11, Z8000 or 8086) or 128KB (for word addressed, like the Xerox Alto's modified Data General Nova model).

[direwolf20]

The writing style appears to be AI.

[FarmerPotato]

I see it all over the article. Occasionally there is a more human voice. (See that single dash? The rare use of "I"?) The overall structure resembles a AI response to "explain this code snippet" prompt.

[ack_complete]

The timeline for fast multiplies is also a bit off, IMUL was already 4c latency / 1c throughput on the Pentium Pro (1995) and Pentium II (1997). Pretty sure IMUL was also only a few cycles on the AMD K6 (1997). Though Intel slowed it back down again in the Pentium 4, until they reverted back to the P6 architecture in the Pentium M.