[Neywiny]

I recommend getting started like the author did: simulation first, then FPGA. Honestly FPGA will take you very far. I always get a kick out of being able to design my own SoC. "Hmmm I need 9 separate I2C ports... Ok, copy block, paste paste paste..." Or if you have an operation in software that's taking forever you can write an accelerator for it

[8f2ab37a-ed6c]

What are the best modern tools to get started with in simulation for those who have never dabbled before?

[Neywiny]

I do the vast majority of my work on xilinx and it's easiest to just use the built in simulator. It's free and supports vhdl and verilog. Most support just one. For lattice and microchip work I use what the tool provides which is usually a cut down modelsim or something

[y1n0]

start here: https://github.com/YosysHQ/oss-cad-suite-build

[sehugg]

Try https://8bitworkshop.com/verilog to get started with dabbling

[sweetjuly]

The other commentator mentioned Verilator (which is indispensable in larger designs) but you may also want to grab Icarus Verilog too. It's a FOSS simulator and, unlike Verilator, is 2-bit and so it handles X ("don't care") and Z ("high impedance") signals. It's ridiculously slow compared to Verilator but the greater fidelity can be valuable depending on what you're trying to do.

[vanjoe]

Verilator is very good. It's faster than anything else, and it is free. The downsides are it won't stimulate encrypted IP blocks. And it doesn't do mixed language sim, so vhdl is no bueno.

[alfiedotwtf]

Are there any open or at least standard FPGAs that the open source community flock to? Last time I looked into FPGAs, it was mostly closed architecture and proprietary tools

[RossBencina]

One flock-to is Lattice ICE40 series. Decent support from Yosys for hobby stuff at least. Possibly Go-win. You can develop for many of the affordable FPGAs with free versions of the proprietary tools. As for "closed architecture" it depends what you mean, the architecture of all FPGAs that I know of is documented, the tools show you how your design was mapped onto the hardware. The proprietary stuff includes the timing model that drives the static timing analysis and timing-aware place and route.

[Neywiny]

Not for anything mid to higher range, but I believe there's open source tooling for some of the older Lattice and Xilinx parts. I would say for me it's not as big a deal as on the software side, because each vendor's hardware tends to be pretty different from each other anyway.

[alfiedotwtf]

Dang, sounds like there’s still a bit of lock in. That’sa shame

[Neywiny]

I think there will always be vendor lock in. The same way there have been architectural differences between Intel and AMD's x86, or even stuff like one specific chip/family tanking performance because one instruction was implemented differently, you won't be able to guarantee efficient utilization of different vendor/families.

For example, I've taken code optimized for Xilinx, ran it for another vendor, and resource count ballooned because stuff that was built-in/free on one wasn't on the other. It's a lot of work to truly make generic code and usually just means switching out modules per vendor.

[checker659]

Do you know if there are any tutorials that use bounded model checking tools from the very get go? For verilog or VHDL.