[Tuna-Fish]

You seem to be mixing up several different levels of caching. Firstly, instructions are primarily fit in the instruction cache, not the data cache.

Secondly, there is no signifcant address translation overhead and the os doesn't need to do any decision making (or well, it does, but it is cached in the TLB and code TLBs are so efficienct nowadays that you can expect the cost to be null) so long as the resident set fits in the main ram -- whether it fits in the cache or not is irrelevant.

Thirdly, just how does the disklessness of the system have any influence? I am not entirely sure but it seems you are somehow mixing up the page cache and the CPU cache, which are completely different things.