[bArray]

> Operating at such low voltages introduces timing challenges, including potential setup time violations. Upbeat addresses these with a second key innovation: a proprietary Error Detection and Correction (EDAC) architecture. This system, which includes a patented special flip-flop design, can catch and correct setup time violations that may occur at near-threshold voltages. This allows for reliable operation without sacrificing efficiency gains.

Wouldn't it be simpler to initialise at a higher voltage and then bring down the voltage after stabilisation? Unless of course the errors are always occurring?

[drob518]

Set up time is needed before every clock edge to ensure reliable state transitions by traditional flip flops. It’s not a one time thing. When you’re operating at low voltages it’s more likely that random system noise will violate the stable level required during the setup time. That’s why they need to do this correction all the time.