[tgma]

The referred paper C isn't a low level language - your computer isn't a fast PDP11[1] was not really addressing multicore parallelism. It was discussing instruction-level parallelism, which is done within an execution thread and is achieved by speculative and out-of-order execution of instructions that do not have sequential dependency on previous instructions.

[1] https://queue.acm.org/detail.cfm?id=3212479

[ookdatnog]

The article does go into cache coherency which is very much intertwined with multicore parallellism:

> The cache coherency protocol is one of the hardest parts of a modern CPU to make both fast and correct. Most of the complexity involved comes from supporting a language in which data is expected to be both shared and mutable as a matter of course.

I feel like we live in a world where everyone works very hard to pretend that C is our best low-level language, when in reality an APL-like purely functional array language would be a better candidate.

[tgma]

Fair enough, though I still think even there the headspace of the author was more in line with proving single-threaded C virtual machine model does not map to how CPU actually behaves, not that a natively parallel language would be best suited to model a contemporary multicore or data parallel processor.

[Peteragain]

APL? Sure, but CSP perhaps? ... I am going to have to think about a FPGA implementation of APL... perhaps..