[kragen]

Claire Wolf's PicoRV32 seems to get a lot of "simple and synthesizable RISC-V design to run on a cheap FPGA" use, although that's more typically for much cheaper FPGA's than an Artix A7, like an iCE40. SeRV is even cheaper and simpler but much slower. Graeme Smecher’s RVC-first "Minimax" is almost as simple as SeRV but not nearly as slow.

I haven't tried any of them, though, so take this with a Himalayan salt lamp.

[jhallenworld]

I've been getting tremendous use out of PicoRV32- it works, it's tiny, and for many use cases ("management plane") you just don't need much speed. I work around its slowness by providing things like relatively large communication buffers in the FPGA. I use it in "execute in place" mode from external SPI-flash (the FPGA's config flash), but with an instruction cache. It can do floating point via emulation which is handy for printf.

I've been meaning to update my toolbox to at least a pipelined processor of some sort (to up the IPC rate to at least 1), but so far just had no strong need. For applications that really need CPU power, I use SoC FPGAs like Zynq.