[cogman10]

But wait, how do you know that's what this is?

The reason I'm negative is the entire article has zero detail on WTF this instruction set is or does. The best you can do is guess from the name of the instruction set.

Compare the linked iPhone article to this blog and you'll quickly see the difference. There's very real discussion in the MTE article of how the instructions work and what they do. This article just says "Memory safety is hard and we'll fix it with these new instructions that fix memory safety!"

[tdullien]

So there's a long intellectual history behind these technologies, and Intel had multiple chances of taking the leadership on this around 2018 - they failed to do so, some of the talent went to Apple, and now Intel has to play catch-up.

I'm pretty certain it'll be the x86 variant of either MTE or MIE.

[linksnapzz]

This is how, amongst other things, IBM POWER cpus do memory tagging for capability-based security on iSeries/OS400.

IIRC, later SPARC64 chips also had a version of this.

[fweimer]

According to this: https://www.devever.net/~hl/ppcas the POWER approach is not a true hardware capability architecture (“nothing about these ISA extensions provides any kind of security invariant against a party which can generate arbitrary machine code”). It's just something that helps software to store one bit per 128 bits of data on the side (plus some other weirdness about load-with-offset instructions).

(SPARC ADI is similar, machine code is still trusted.)

[pjmlp]

ADI, since 2015, still shipping.

[helloooooooo]

The x64 Windows Kernel is starting to get support for this. There are a few references to memory tagging appearing in the public symbol files.

[eigenform]

Probably because it's very likely that both AMD and Intel have had engineers working on this sort of thing for a long time, and they're now deciding to collectively hash out whatever the solution is going to be for both of them.

[zdw]

Better to have this than two sets of instruction, as is currently the case for virtualization entry/exit points on amd64 platforms.

[DannyBee]

A lot of this sort of thing come from AMD/Intel clients, rather than internally.

In this particular case, it definitely does :)

[DannyBee]

>But wait, how do you know that's what this is?

A lot of these extensions come from Intel/AMD/etc clients first, and because of how long it takes a thing to make it into mainstream chips, it was probably conceived of and worked on at least 5 years ago, often longer.

This particular thing has a long history and depending on where they worked, they know about that history.

However, they are often covered by extra layers of NDA's on top of whatever normal corporate employee NDA you have, so most people won't say a ton about it.

[fweimer]

I don't know if it is intended this way, but there's one useful outcome even with the limited amount of detail disclosed:

There are industry partners who work closely with AMD and Intel (with on-site partner engineers etc.), but who are not represented in the x86 ecosystem advisory group, or maybe they have representation, but not at the right level. If these industry partners notice the blog post and they think they have technology in impacted areas, they can approach their contacts, asking how they can get involved.