[jeffbee]

The abstraction is the problem. Get rid of the translation layer, manage flash directly in the operating system, and suddenly the ambiguity dissolves. You would get meaningful, uniform statistics with semantics necessarily matching those used by your operating system.

[ssl-3]

Do I really want my relatively expensive general-purpose CPU to be burdened with the task of managing flash using software, when a relatively inexpensive ASIC does that job very quickly and efficiently?

There's a lot of non-trivial stuff that goes on inside of a modern SSD. And to be sure, none of it is magic; all of it could certainly be implemented in software.

But is that kind of drastic move strictly necessary in order to get meaningful statistics?

[jeffbee]

There would be other benefits, such as reduced write amplification and better workload isolation. The observability would just be gravy.

[adgjlsfhk1]

ssds aren't using Asics. they're full blown computers. Apple has moved to ssd control on soc and it seems to work for them.

[ssl-3]

Apple moving SSD control to a hardware block in their own custom chip is not the same thing as implementing the functionality using software.

(You've heard about apple and orange comparisons, right? Right.)

[1718627440]

I would call that thing running on that custom chip software.

[ssl-3]

You don't need me or anyone else to tell you that you're free to call it whatever you want.

I'm going to keep referring to the QuickSync video encoding block in my CPU as "hardware," though, because the tiny lump of transistors that is dedicated to performing this specialized task is something that I can kick.

Relatedly, the business of managing raw NAND storage on Apple devices and abstracting it to operating system software as NVMe: That translation happens in hardware. That hardware is also something that I can kick, so I'm going to keep calling it "hardware".

[kasabali]

QuickSync isn't analog to an SSD controller. One is a specialized IP block that handles video streams, other is a generic ARM or RISC core running a specific software for handling low level NAND operations.