[benob]

Is there anything preventing them from using heterogeneous memory chips, like 1/4 GDDR7 and 3/4 LPDDR? It could enable new MEO-like architectures with finer-grained performance tuning for long contexts.

[vetrom]

You'd have to burn more die space for the duplicate but different ram controller logic and cache trees, I bet.

If the internal bus architecture is anything similar to QPI, getting the 'different' parts to communicate reliably is probably also a pain.