[snvzz]

It is a trade-off they chose, and they have to pay for it by requiring a larger cache. I argue it wasn't a good choice.

They're not getting significantly simpler decoders, relative to RISC-V which chose the other route i.e. variable instruction length with parallelized decoder simplicity in mind.

They also do worse in other metrics e.g. longer interdependent instruction chains.

Still generally better than x86, but that's a really low bar to meet.