[arp242]

Do RISC architectures still exist? ARM has gained tons of stuff and isn't really "RISC" any more either.

Maybe RISC-V? It's right there in the name, but I haven't really looked at it. However, there are no RISC-V chips that have anywhere near the performance x86 or ARM has, so it remains to be seen if RISC-V can be competitive with x86 or ARM for these types of things.

RISC is one of those things that sounds nice and elegant in principle, but works out rather less well in practice.

[userbinator]

MIPS is as close to a "real RISC" CPU as one can be, and it's "everywhere you don't look", but for reasons entirely unrelated to performance --- it's the choice of SoCs which are too cheap for ARM. I suspect RISC-V is going to become more popular in that market, although it's one which is already filled with various Chinese MIPS/RISC-ish cores that are entirely unimpressive.

[remexre]

> Maybe RISC-V?

RISC-V is specified as a RISC (and allows very space-/power-efficient lower-end designs with the classic RISC design), but designed with macro-op fusion in mind, which gets you closer to a CISC decoder and EUs.

It's a nice place to be in tooling-wise, but it seems too early to say definitively what extensions will need to be added to get 12900K/9950X/M4 -tier performance-per-core.

In either case though, a bunch of the tricks that make modern CPUs fast are ISA-independent; stuff like branch prediction or [0] don't depend on the ISA, and can "work around" needing more instructions to do certain tasks, for one side or the other.

[0]: https://tavianator.com/2025/shlx.html