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by variaga
341 days ago
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Word. 28 years of FPGA and ASIC design here, in VHDL, Verliog and SystemVerliog. Coming from VHDL, verilog had some painful limitations (no struct/record type) but SV fixed those, and supports some surprisingly powerful metaprogramming. But even when using plain verilog the language was never the limiting factor on the design process. |
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